1. Technical Field
The present invention relates to integrated circuits in general, and in particular to an integrated circuit having multiple repeatable circuit elements. Still more particularly, the present invention relates to a method for connecting repeatable circuit elements within an integrated circuit for reducing single-event upsets.
2. Description of Related Art
In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, integrated circuits are more susceptible to single-event upsets (SEUs) or soft errors than they would have otherwise in terrestrial environments. SEUs are typically caused by electron-hole pairs generated by a single energetic particle as the single energetic particle passes through various circuit elements within an integrated circuit. If the energetic particle generates a critical amount of charges in a node of a circuit element within the integrated circuit, the logic state of the node will be upset.
As technology scales to smaller geometries, the sizes of circuit elements within integrated circuit also become smaller. As a result, the spacing between nodes within a circuit element is reduced to a level that allows charges deposited from a single-event hit to be collected simultaneously by two nodes within an circuit element. Such phenomenon creates a special sensitivity that drastically reduces the effectiveness of SEU hardened circuits. The problem of simultaneously collection of charges by two nodes cannot be resolved simply by increasing of the nodal spacing because it will defect the advantages of technology scaling in achieving higher density integrated circuits.
Consequently, it would be desirable to provide an improved method for connecting circuit elements within an integrated circuits for reducing SEUs.